The present invention relates to computer logic circuits and, more particularly, to an array of multi-master single-slave flip-flop circuits which may be disposed on a single large-scale integrated circuit chip.
In conventional practice, two substantially identical latching circuits of the two-level cascode emitter-coupled logic type may be coupled together in series on a single integrated circuit chip. The first latching circuit serves as a master flip-flop, and the second latching circuit serves as a slave flip-flop. This master-slave combination has the advantage that it stores data reliably on the edge of a clock pulse, that is, at the clock pulse transition. Further, this master-slave arrangement provides the sequence master acquire then slave release which ensures that the output will change only if the new data stored in the master differs from data stored previously in the slave. This arrangement also provides the sequence slave latch then master release which ensures that data stored in the master will be captured in the slave before the master is released to acquire new data.
However, when it is desired to use the master-slave flip-flop in certain applications such as a J-K type flip-flop for example, feedback from the output to the input is necessary and the data input is a nontrivial logic function of external and fed back input signals. To implement the required logic function in conventional practice, a three-decision level cascode circuit may be employed as the latching circuit for the master flip-flop. However, in situations where the chip temperature varies over a wide range and the voltage supply is not abnormally regulated, this circuit arrangement is not reliable.
Alternatively in conventional practice, input gating to two-level cascode master-slave circuits may be performed by one or more external gating networks in series with the input. This arrangement has the disadvantage that a time delay is introduced which results in a slower speed.
More generally for operation over restricted temperature ranges both two-level and three-level cascode circuits have been coupled together to form single-master single-slave flip-flops. However, to perform specific logic functions, external gating networks typically have been used. Such is the case in conventional multiplexer and universal counter cells, for example. With the extra gating stage, the circuits are slower due to a time delay or propagation delay introduced by the external gating network.
Additionally, in some prior applications, a single three-level cascode master/single slave configuration was used in place of an external gating network/single two-level master/single slave configuration. The former configuration eliminates the gating delay but if operated under extreme temperature conditions, such as in a military type environment, or if power supply voltages are not held stable, the circuit may malfunction. For instance, at or near -40.degree. C., a three-level cascode circuit may become inoperative if the power supply voltage changes from -5.2 to -4.8 volts.